To secure a sufficient cell capacitance in a limited area for integrated circuit devices, such as dynamic random access memories (DRAMs), various techniques may be used. Examples of such techniques include using a high dielectric material for a dielectric layer, reducing the thickness of a dielectric layer, and increasing the effective area of lower electrodes. The technique of using the high dielectric material may require the introduction of new equipment, examining the reliability and mass productivity of the dielectric layer, and/or lowering the temperature of succeeding processes, which may require additional material and time. Consequently, because the technique of increasing the effective area of the lower electrodes may allow the existing dielectric layer to be used, and because the technique may be carried out using existing processes, this technique may offer the most promise for application to existing processes.
To increase the effective area of the lower electrodes, a method of forming three-dimensional lower electrodes, such as cylindrical lower electrodes or fin type lower electrodes, a method of growing hemispherical grain (HSG) on the lower electrodes, and/or a method of increasing the height of the lower electrodes may be used. The method of growing the HSG may obstruct the securing of a critical dimension (CD) between the lower electrodes. In addition, the HSG may detach from the lower electrodes and cause bridges between the lower electrodes, which can make it difficult to apply the method of growing the HSG to an integrated circuit device having a design rule of less than 0.14 μm. Accordingly, the methods of forming three-dimensional lower electrodes and increasing the height of the lower electrodes are commonly used to increase the effective area of lower electrodes.
Although the method of forming three-dimensional lower electrodes, such as the cylindrical lower electrodes, is generally resistant to errors because it secures a sufficient charge storage area, it may be difficult to form the cylindrical lower electrodes. In an integrated one-cylinder storage (OCS) structure, to increase the height of the lower electrodes to secure a sufficient capacitance for operating the device, a thick mold oxide may be used. In this case, steep slopes may be generated in etching node holes in which the lower electrodes will be formed so that CDs of the bottom portions of the storage node holes are reduced. Consequently, the thin and tall lower electrodes may have narrow bottoms that result in an unstable profile. Furthermore, weak lower electrodes may fall down and break due to thermal stress, which is generated in succeeding processes, thereby causing bridges between cells. As a result, defects may occur in the devices.
Meanwhile, the method of increasing the height of the lower electrodes may result in a significant step difference between a cell region having capacitors and a peripheral circuit region without the capacitors. Consequently, the method of increasing the height of a lower electrode may involve planarization of an intermetal dielectric (IMD), which is formed on a resultant structure containing the capacitors, to perform a succeeding metal interconnection process.
A typical method for planarizing the IMD involves the following operations: forming and reflowing a boron phosphorus silicate glass (BPSG) layer as an IMD, forming a thick IMD layer, etching portions of the IMD layer on a cell region to reduce a step difference between the cell region and a peripheral circuit region, and planarizing the remaining IMD layer on the cell region by chemical mechanical polishing (CMP). Because the reflow process is performed at a relatively high temperature, the characteristics of transistors in a highly integrated device may deteriorate due to thermal stress and the resistance of a contact region may increase. In addition, the etching and CMP processes may be complicated.